The present invention relates to a method and an apparatus for laying out a power wiring of a semiconductor device.
In digital circuits on which a number of logic circuits are mounted, power-supply noise occurs due to switching operation of logic circuits. In particular, in analog-digital-mixed LSIs on which analog circuits and digital circuits are mounted together on a single substrate, the power-supply noise due to digital circuits reaches analog circuits through the substrate, which causes a malfunction of analog circuits. Such power-supply noise transmitted through the substrate is particularly called substrate noise.
Therefore, it is important to reduce the substrate noise in the circuit design. By simply increasing the distance between an analog circuit and a digital circuit, the substrate noise is reduced. However, the size of an LSI becomes larger. Thus, a guard ring is provided around the analog circuit, for example. Su et al. (“Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits,” IEEE Journal of Solid-State Circuits, vol. 28, no. 4, pp. 420-430, Apr. 1993.) discloses a circuit simulation method for an analog-digital-mixed LSI having guard rings. However, the chip area and manufacturing processes are increased by providing guard rings.
Further, the substrate noise can also be reduced by providing decoupling capacitors to the digital circuit. Japanese Unexamined Patent Application Publication No. 2006-172488 discloses a circuit design method for providing decoupling capacitors effectively. However, the chip area and the power consumption due to leak current are increased by providing decoupling capacitors.
On the other hand, the substrate noise can be considered as a dynamic IR drop problem because the substrate noise is caused due to variations in power voltage. Thus, as in the case of solving the dynamic IR drop problem, the substrate noise can also be reduced by widening the power wiring of the digital circuit. Singh et al. (“Partition-Based Algorithm for Power Grid Design Using Locality,” IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 25, no. 4, pp. 664-677, Apr. 2006.) discloses a method for resolving the IR drop violation by widening the whole wiring in a certain region when the IR drop violation exists.
Note that Japanese Unexamined Patent Application Publication No. 2009-276822 discloses a design support method of a semiconductor device for facilitating the analysis of the substrate noise which was invented by the present inventor.